Journal: Micromachines

Article Title: Implementation of Field-Programmable Gate Array Platform for Object Classification Tasks Using Spike-Based Backpropagated Deep Convolutional Spiking Neural Networks

doi: 10.3390/mi14071353

Figure Lengend Snippet: Literature review of works deploying SNNs and hybrid networks on FPGA platforms alongside this study.

Article Snippet: An Intel i7-12700 CPU and Xilinx Kintex UltraScale FPGA (xcku115-flvf1924-2-i) were used to run the DCSNNs with input images taken from all the datasets.

Techniques: Multiplexing

Journal: Micromachines

Article Title: Implementation of Field-Programmable Gate Array Platform for Object Classification Tasks Using Spike-Based Backpropagated Deep Convolutional Spiking Neural Networks

doi: 10.3390/mi14071353

Figure Lengend Snippet: FPGA design elements.

Article Snippet: An Intel i7-12700 CPU and Xilinx Kintex UltraScale FPGA (xcku115-flvf1924-2-i) were used to run the DCSNNs with input images taken from all the datasets.

Techniques:

Journal: Micromachines

Article Title: Implementation of Field-Programmable Gate Array Platform for Object Classification Tasks Using Spike-Based Backpropagated Deep Convolutional Spiking Neural Networks

doi: 10.3390/mi14071353

Figure Lengend Snippet: Performance of TSSL-BP (rows 1 and 2) and SGD-BP (rows 3 and 4) on the MNIST dataset.

Article Snippet: An Intel i7-12700 CPU and Xilinx Kintex UltraScale FPGA (xcku115-flvf1924-2-i) were used to run the DCSNNs with input images taken from all the datasets.

Techniques:

Journal: Micromachines

Article Title: Implementation of Field-Programmable Gate Array Platform for Object Classification Tasks Using Spike-Based Backpropagated Deep Convolutional Spiking Neural Networks

doi: 10.3390/mi14071353

Figure Lengend Snippet: Performance of TSSL-BP (rows 1 and 2) and SGD-BP (rows 3 and 4) on the CIFAR10 dataset.

Article Snippet: An Intel i7-12700 CPU and Xilinx Kintex UltraScale FPGA (xcku115-flvf1924-2-i) were used to run the DCSNNs with input images taken from all the datasets.

Techniques:

Journal: Micromachines

Article Title: Implementation of Field-Programmable Gate Array Platform for Object Classification Tasks Using Spike-Based Backpropagated Deep Convolutional Spiking Neural Networks

doi: 10.3390/mi14071353

Figure Lengend Snippet: Performance of TSSL-BP (rows 1 and 2) and SGD-BP (rows 3 and 4) on the KITTI dataset.

Article Snippet: An Intel i7-12700 CPU and Xilinx Kintex UltraScale FPGA (xcku115-flvf1924-2-i) were used to run the DCSNNs with input images taken from all the datasets.

Techniques:

Journal: Micromachines

Article Title: Implementation of Field-Programmable Gate Array Platform for Object Classification Tasks Using Spike-Based Backpropagated Deep Convolutional Spiking Neural Networks

doi: 10.3390/mi14071353

Figure Lengend Snippet: Performance of TSSL-BP (rows 1 and 2) and SGD-BP (rows 3 and 4) on the INHA_ADAS dataset.

Article Snippet: An Intel i7-12700 CPU and Xilinx Kintex UltraScale FPGA (xcku115-flvf1924-2-i) were used to run the DCSNNs with input images taken from all the datasets.

Techniques:

Journal: Micromachines

Article Title: Implementation of Field-Programmable Gate Array Platform for Object Classification Tasks Using Spike-Based Backpropagated Deep Convolutional Spiking Neural Networks

doi: 10.3390/mi14071353

Figure Lengend Snippet: Performance of TSSL-BP (rows 1 and 2) and SGD-BP (rows 3 and 4) on the INHA_KLP dataset.

Article Snippet: An Intel i7-12700 CPU and Xilinx Kintex UltraScale FPGA (xcku115-flvf1924-2-i) were used to run the DCSNNs with input images taken from all the datasets.

Techniques:

Journal: Micromachines

Article Title: Implementation of Field-Programmable Gate Array Platform for Object Classification Tasks Using Spike-Based Backpropagated Deep Convolutional Spiking Neural Networks

doi: 10.3390/mi14071353

Figure Lengend Snippet: Performance analysis of the current study alongside other works with respect to MNIST dataset.

Article Snippet: An Intel i7-12700 CPU and Xilinx Kintex UltraScale FPGA (xcku115-flvf1924-2-i) were used to run the DCSNNs with input images taken from all the datasets.

Techniques:

Journal: Micromachines

Article Title: Implementation of Field-Programmable Gate Array Platform for Object Classification Tasks Using Spike-Based Backpropagated Deep Convolutional Spiking Neural Networks

doi: 10.3390/mi14071353

Figure Lengend Snippet: Performance analysis of the current study alongside other works with respect to CIFAR10 dataset.

Article Snippet: An Intel i7-12700 CPU and Xilinx Kintex UltraScale FPGA (xcku115-flvf1924-2-i) were used to run the DCSNNs with input images taken from all the datasets.

Techniques:

Journal: Micromachines

Article Title: Implementation of Field-Programmable Gate Array Platform for Object Classification Tasks Using Spike-Based Backpropagated Deep Convolutional Spiking Neural Networks

doi: 10.3390/mi14071353

Figure Lengend Snippet: Power efficiency of FPGA (xcku115-flvf1924-2-i) compared to CPU (Intel i7-12700).

Article Snippet: An Intel i7-12700 CPU and Xilinx Kintex UltraScale FPGA (xcku115-flvf1924-2-i) were used to run the DCSNNs with input images taken from all the datasets.

Techniques:

Journal: Micromachines

Article Title: Implementation of Field-Programmable Gate Array Platform for Object Classification Tasks Using Spike-Based Backpropagated Deep Convolutional Spiking Neural Networks

doi: 10.3390/mi14071353

Figure Lengend Snippet: FPGA (xcku115-flvf1924-2-i) power utilization in dynamic mode (deploying DCSNNs).

Article Snippet: An Intel i7-12700 CPU and Xilinx Kintex UltraScale FPGA (xcku115-flvf1924-2-i) were used to run the DCSNNs with input images taken from all the datasets.

Techniques: